Digit-serial Reconfigurable Fpga Logic Block Architecture

This paper presents a novel eld-programmable gate array logic block architecture which incorporates support for digit-serial DSP architectures on a digit wide basis, without diminishing the support for random and control logic applications. To eeciently realize a digit-serial DSP design on FPGAs, one must create an FPGA architecture optimized for those types of systems. Key to the suitability of the FPGA for these applications is the fact that each of its basic blocks is capable of processing a digit-size of up to 4-bits. A novel digit-serial FPGA logic block architecture has been proposed to satisfy the requirement of rapid prototyping and eecient implementation of digit-serial DSP applications. Digit-serial DSP designs using the digit-serial FPGA are compared to those implemented on a Xilinx FPGA chip. The results show that the normalized area of digit-serial circuits on the DS-FPGA is only 33 54% of the number required on the Xilinx FPGA.